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MT3170B/71B, MT3270B/71B, MT3370B/71B Wide Dynamic Range DTMF Receiver
Data Sheet Features
* * * * * * * * * Wide dynamic range (50 dB) DTMF Receiver Call progress (CP) detection via cadence indication 4-bit synchronous serial data output Software controlled guard time for MT3x70B Internal guard time circuitry for MT3x71B Powerdown option (MT317xB & MT337xB) 4.194304 MHz crystal or ceramic resonator (MT337xB and MT327xB) External clock input (MT317xB) Guarantees non-detection of spurious tones Ordering Information
MT3170/71BE MT3270/71BE MT3370/71BS MT3370/71BN MT3370/71BSR MT3371BNR MT3270/71BE1 MT3171BE1 MT3170BE1 MT3370/BN1 MT3370/71BS1 MT3370/71BSR1 8 Pin PDIP 8 Pin PDIP 18 Pin SOIC 20 Pin SSOP 18 Pin SOIC 20 Pin SSOP 8 Pin PDIP* 8 Pin PDIP* 8 Pin PDIP** 20 Pin SSOP* 18 Pin SOIC* 18 Pin SOIC* *Pb Free Matte Tin **Pb Free Tin/Silver/Copper -40C to 85C Tubes Tubes Tubes Tubes Tape & Reel Tape & Reel Tubes Tubes Tubes Tubes Tubes Tape & Reel
August 2005
Applications
* * * Integrated telephone answering machine End-to-end signalling Fax Machines
PWDN VDD VSS
Voltage Bias Circuit
Steering Circuit High Group Filter Antialias Filter Dial Tone Filter Low Group Filter Digital Detector Algorithm Code Converter and Latch
Digital Guard Time Parallel to Serial Converter & Latch
ESt or DStD
ACK
INPUT
AGC
Mux
SD
OSC2 OSC1 (CLK)
Oscillator and Clock Circuit To All Chip Clocks
Energy Detection
MT3170B/71B and MT337xB only. MT3270B/71B and MT337xB only. MT3x71B only.
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1995-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT3170B/71B, MT3270B/71B, MT3370B/71B
Description
Data Sheet
The MT3x7xB is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope) of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without additional components. A power-down option is provided for the MT317xB and MT337xB.
MT3170B/71B INPUT PWDN CLK VSS 1 2 3 4 8 7 6 5 VDD INPUT ESt/ DStD OSC2 ACK SD OSC1 VSS
MT3270B/71B 1 2 3 4 8 7 6 5 VDD ESt/ DStD ACK SD NC INPUT PWDN OSC2 NC OSC1 NC NC VSS
MT3370B/71B 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD NC NC ESt/DStD NC ACK NC SD NC NC NC INPUT PWDN NC OSC2 OSC1 VSS NC NC
MT3370B/71B 1 2 3 4 5 6 7 8 9 10 20 PIN SSOP 20 19 18 17 16 15 14 13 12 11 NC NC VDD NC ESt/DStD NC ACK SD NC NC
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
Figure 2 - Pin Connections Pin Description Pin # 337xB 2 4 6 327xB 1 2 3 317xB 1 3 Name INPUT OSC2 OSC1 (CLK) Description DTMF/CP Input. Input signal must be AC coupled via capacitor. Oscillator Output. Oscillator/Clock Input. This pin can either be driven by: 1) an external digital clock with defined input logic levels. OSC2 should be left open. 2) connecting a crystal or ceramic resonator between OSC1 and OSC2 pins. Ground. (0V) Serial Data/Call Progress Output. This pin serves the dual function of being the serial data output when clock pulses are applied after validation of DTMF signal, and also indicates the cadence of call progress input. As DTMF signal lies in the same frequency band as call progress signal, this pin may toggle for DTMF input. The SD pin is at logic low in powerdown state. Acknowledge Pulse Input. After ESt or DStD is high, applying a sequence of four pulses on this pin will then shift out four bits on the SD pin, representing the decoded DTMF digit. The rising edge of the first clock is used to latch the 4-bit data prior to shifting. This pin is pulled down internally. The idle state of the ACK signal should be low.
9 11
4 5
4 5
VSS SD
13
6
6
ACK
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
Pin Description Pin # 337xB 15 327xB 7 317xB 7 Name ESt
(MT3x70B)
Data Sheet
Description Early Steering Output. A logic high on ESt indicates that a DTMF signal is present. ESt is at logic low in powerdown state. Delayed Steering Output. A logic high on DStD indicates that a valid DTMF digit has been detected. DStD is at logic low in powerdown state. Positive Power Supply (5 V Typ.) Performance of the device can be optimized by minimizing noise on the supply rails. Decoupling capacitors across VDD and VSS are therefore recommended. No Connection. Pin is unconnected internally.
DStD
(MT3x71B)
18
8
8
VDD
1,5,7,8, 10, 12, 14,16, 17 3
-
-
NC
-
2
PWDN
Power Down Input. A logic high on this pin will power down the device to reduce power consumption. This pin is pulled down internally and can be left open if not used. ACK pin should be at logic '0' to power down device.
Summary of MT3x70/71B Product Family Device Type MT3170B MT3171B MT3270B MT3271B MT3370B MT3371B 8 Pin 18 Pin 20 Pin PWDN 2 Pin OSC Ext CLK ESt DStD
Functional Description
The MT3x7xBs are high performance and low power consumption DTMF receivers. These devices provide wide dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to separate the input DTMF signal into high and low group tones. The high group and low group tones are then verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection stage, the valid DTMF digit is translated to a 4-bit binary code (via an internal look-up ROM). Data bits can then be shifted out serially by applying external clock pulses. Automatic Gain Control (AGC) Circuit As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With large input signal amplitude (between 0 and approximately -30 dBm for each tone of the composite signal), the
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
Data Sheet
AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit. Filter and Decoder Section The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection. The composite dual-tone signal is further split into its individual high and low frequency components by two 6th order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For MT3x70B, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high, indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt pin to go low. For MT3x71B, an internal delayed steering counter validates the early steering signal after a predetermined guard time which requires no external components. The delayed steering (DStD) will go high only when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD output will go low only after this validation period. Energy Detection The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal comparator (-35dBm), the energy detector produces an energy present indication on the SD output. The integrator ensures the SD output will remain at high even though the input signal is changing. When the input signal is removed, the SD output will go low following the integrator decay time. Short decay time enables the signal envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification. As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse applied at the ACK pin. Serial Data (SD) Output When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The rising edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit on the SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure 5). If less than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be valid. Clock pulses should be applied to clock out any remaining data bits to resume normal operation. Any transitions in excess of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at logic low. The 4-bit binary representing all 16 standard DTMF digits are shown in Table 1.
FLOW FHIGH DIGIT b3 b2 b1 b0
697 697 697 770 770 770 852
1209 1336 1477 1209 1336 1477 1209
1 2 3 4 5 6 7
0 0 0 0 0 0 0
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
FLOW FHIGH DIGIT b3 b2 b1 b0
Data Sheet
852 852 941 941 941 697 770 852 941
1336 1477 1336 1209 1477 1633 1633 1633 1633
8 9 0 * # A B C D
1 1 1 1 1 1 1 1 0
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
0= LOGIC LOW, 1= LOGIC HIGH
Table 1 - Serial Decode Bit Table
Note: b0=LSB of decoded DTMF digit and shifted out first.
Powerdown Mode (MT317xB/337xB) The MT317xB/337xB devices offer a powerdown function to preserve power consumption when the device is not in use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 2). ACK (input) low low high high
+
PWDN (input) low high+ low high
ESt/DStD (output) Refer to Fig. 4 for timing waveforms low low undefined Table 2 - Powerdown Mode
SD (output) Refer to Fig. 4 for timing waveforms low undefined undefined
MT317xB/337xB status normal operation powerdown mode undefined undefined
=enters powerdown mode on the rising edge.
Frequency 1 (Hz) 350 425 400 480 440 480 440 480
Frequency 2 (Hz) 440 ----620 --620 480 620
On/Off continuous continuous continuous 0.5s/0.5s 0.5s/0.5s 0.25s/0.25s 2.0s/4.0s 0.25s/0.25s
Description North American Dial Tones European Dial Tones Far East Dial Tones North American Line Busy Japanese Line Busy North American Reorder Tones North American Audible Ringing North American Reorder Tones
Table 3 - Call Progress Tones
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
Parameter R1 L1 C1 C0 Qm f
Note:
Data Sheet
Unit Ohms mH pF pF %
Resonator 6.580 0.359 4.441 34.890 1.299E+03 0.2%
Crystal 150 95.355 15.1E-03 12.0 101.2E+ 03 0.01%
Table 4 - Recommended Resonator and Crystal Specifications
Qm=quality factor of RLC model, i.e., 1/2PR1C1.
L1
C1
R1
C0 R1 = Equivalent resistor. L1 = Equivalent inductance. C1 = Equivalent compliance. C0 = Capacitance between electrode.
Resonator and Crystal Electric Equivalent Circuit Oscillator The MT327xB/337xB can be used in both external clock or two pin oscillator mode. In two pin oscillator mode, the oscillator circuit is completed by connecting either a 4.194304 MHz crystal or ceramic resonator across OSC1 and OSC2 pins. Specifications of the ceramic resonator and crystal are tabulated in Table 4. It is also possible to configure a number of these devices employing only a single oscillator crystal. The OSC2 output of the first device in the chain is connected to the OSC1 input of the next device. Subsequent devices are connected similarly. The oscillator circuit can also be driven by an 4.194304 MHz external clock applied on pin OSC 1. The OSC2 pin should be left open. For MT317xB devices, the CLK input is driven directly by an 4.194304 MHz external digital clock.
Applications
The circuit shown in Figure 3 illustrates the use of a MT327xB in a typical receiver application. It requires only a coupling capacitor (C1) and a crystal or ceramic resonator (X1) to complete the circuit. The MT3x70B is designed for user who wishes to tailor the guard time for specific applications. When a DTMF signal is present, the ESt pin will go high. An external microcontroller monitors ESt in real time for a period of time set by the user. A guard time algorithm must be implemented such that DTMF signals not meeting the timing requirements are rejected. The MT3x71B uses an internal counter to provide a preset DTMF validation period. It requires no external components. The DStD output high indicates that a valid DTMF digit has been detected. The 4.194304 MHz frequency has a secondary advantage in some applications where a real time clock is required. A 22-bit counter will count 4,194,304 cycles to provide a one second time base.
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
Data Sheet
C1 DTMF/CP Input
VDD 1 INPUT MT327xB 2 OSC2 OSC1 VSS ESt/DStD ACK SD 7 6 5 To microprocessor or microcontroller VDD 8
X1
3 4
COMPONENTS LIST: C1 = 0.1 F 10 % X1 = Crystal or Resonator (4.194304 MHz)
Figure 3 - Application Circuit for MT327xB
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
Absolute Maximum Ratings - Voltages are with respect to VSS=0V unless otherwise stated. Parameter 1 2 3 4 5 DC Power Supply Voltage Voltage on any pin (other than supply) Current at any pin (other than supply) Storage temperature Package power dissipation Symbol VDD-VSS VI/O II/O TS PD -65 -0.3 Min. Max. 6 6.3 10 150 500
Data Sheet
Units V V mA C mW
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS=0V unless otherwise stated Parameter 1 2 3 4 Positive Power Supply Oscillator Clock Frequency Oscillator Frequency Tolerance Operating Temperature Sym. VDD fOSC fOSC Td -40 25 Min. 4.75 Typ. 5.0 4.194304 0.1 85 Max. 5.25 Units V MHz % C Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to VDD=5V5%,VSS=0V, and temperature -40 to 85C, unless otherwise
stated.
Characteristics 1 2 3a 3b 4a 4b 5 6 Operating supply current Standby supply current Input logic 1 Input logic 1 (for OSC1 input only) Input logic 0 Input logic 0 (for OSC1 input only) Input impedance (pin 1) Pull-down Current (PWDN, ACK pins) Output high (source) current Output low (sink) current
Sym. IDD IDDQ VIH VIH VIL VIL RIN IPD
Min.
Typ. 3 30
Max. 8 100
Units mA A V V
Test Conditions
PWDN=5V, ACK=0V ESt/DStD = SD = 0V MT327xB/MT337xB
4.0 3.5 1.0 1.5 50 25
V V kW mA with internal pull-down resistor of approx. 200 k. PWDN/ACK = 5V VOUT=VDD-0.4V VOUT=VSS+0.4V MT327xB/MT337xB
7 8
IOH IOL
0.4 1.0
4.0 9.0
mA mA
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
Data Sheet
AC Electrical Characteristics - voltages are with respect to VDD=5V5%, VSS=0V and temperature -40 to +85C unless otherwise
stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 Valid input signal level (each tone of composite signal) Positive twist accept Negative twist accept Frequency deviation accept Frequency deviation reject Third tone tolerance Noise tolerance Dial tone tolerance Supervisory tones detect level (Total power) Supervisory tones reject level Energy detector attack time Energy detector decay time
Sym.
Min. -50 2.45
Typ.
Max. 0 775 8 8
Units dBm mVRMS dB dB
Test Conditions* 1,2,3,5,6,12 1,2,3,4,11,12,15 1,2,3,4,11,12,15 1,2,3,5,12 1,2,3,5,12,15
1.5% 2Hz 3.5% -16 -12 +15 -35 -50 tSA tSD 3 1.0 6.5 25 10 30 50 tDP tDA tREC tREC 20 3 13 3 20 15 40 dB dB dB dBm dBm ms ms ms ms ms ms ms ms ms
1,2,3,4,5,12 7,9,12 8,10,12 16 16 16 16 IDDQ 100A MT3170B/3370B MT3171B/3371B Note 14 MT3x70B MT3x70B MT3x71B MT3x71B
13a Powerdown time 13b Powerup time
14 15 16 17
Tone present detect time (ESt logic output) Tone absent detect time (ESt logic output) Tone duration accept (DStD logic output) Tone duration reject (DStD logic output)
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
stated.
Data Sheet
AC Electrical Characteristics - voltages are with respect to VDD=5V5%, VSS=0V and temperature -40 to +85C unless otherwise Characteristics 18 19 20 21 22 Interdigit pause accept (DStD logic output) Interdigit pause reject (DStD logic output) Data shift rate 40-60% duty cycle Propagation delay (ACK to Data Bit) Data hold time (ACK to SD) Sym. tID tDO fACK tPAD tDH 30 20 1.0 100 50 3.0 140 Min. Typ. Max. 40 Units ms ms MHz ns ns Test Conditions* MT3x71B MT3x71B 13,15 1MHz fACK, 13,15 13,15
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing * Test Conditions 1. dBm refers to a reference power of 1 mW delivered into a 600 ohms load. 2. Data sequence consists of all DTMF digits. 3. Tone on = 40 ms, tone off = 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. Tone pair is deviated by 1.5% 2 Hz. 7. Bandwidth limited (0-3 kHz) Gaussian noise. 8. Precise dial tone frequencies are 350 Hz and 440 Hz ( 2%). 9. Referenced to lowest level frequency component in DTMF signal. 10. Referenced to the minimum valid accept level. 11. Both tones must be within valid input signal range. 12. External guard time for MT3x70B = 20 ms. 13. Timing parameters are measured with 70pF load at SD output. 14. Time duration between PWDN pin changes from `1` to `0` and ESt/DStD becomes active. 15. Guaranteed by design and characterization. Not subject to production testing. 16. Value measured with an applied tone of 450 Hz.
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Zarlink Semiconductor Inc.
MT3170B/71B, MT3270B/71B, MT3370B/71B
tREC
DTMF Tone #n DTMF Tone #n + 1
Data Sheet
tDO
DTMF Tone #n + 1
INPUT
Input Signal
tDP
ESt (MT3x70B)
tDA
tREC
DStD (MT3x71B)
tID
ACK
LSB SD
MSB
LSB
MSB
tSA
tSD
Input Signal Envelope
b0b1b2b3
b0b1b2b3
tDO tID tREC tREC tDA tDP tSA tSD
-
maximum allowable dropout during valid DTMF signals. (MT3x7xB). minimum time between valid DTMF signals (MT3x71B). maximum DTMF signal duration not detected as valid (MT3x7xB). minimum DTMF signal duration required for valid recognition (MT3x71B). time to detect the absence of valid DTMF signals (MT3x70B). time to detect the presence of valid DTMF signals (MT3x70B). supervisory tone integrator attack time (MT3x7xB). supervisory tone integrator decay time (MT3x7xB).
Figure 4 - Timing Diagram
ESt/DStD
1/fACK
VIH ACK VIL
tPAD
VIH VIL
DTMF Energy Detect
tDH
b0 LSB b1 b2 b3 MSB
DTMF Energy Detect
SD
Figure 5 - ACK to SD Timing
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